Data processing



March 22, 1966 L. l.. RAKoczl ETAL DATA PROCESSING Arran/Er March 22,1966 L RAKOCZl ETAL 3,242,349

DATA PROCESSING Filed Nov. 14, 19x62 4 Sheets-Sheet L 80- if. ft f'. 82

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' Tam/M4N@ w y y' 5 i s s 5' EH a HE 00 F/ 0 5 0 Z a L A7540 /A/ A 3f*(aM/mwa United States Patent O 3,242,349 DATA PROCESSING Laszlo LeslieRakoczi, Phoenix, Ariz., and John W. Figueroa, Arcadia, Calif., assgnorsto Radio Corporation of America, a corporation of Delaware Filed Nov.14, 1962, Ser. No. 237,538 6 Claims. (Cl. 307-885) The present inventionrelates to the control of a data processing system such as a digitalcomputer.

In an asynchronous digital data processing system, to achieve maximumoperating speeds, each logic or other asynchronous stage should initiateits operation immediately upon the completion of the operation of thepreceding stage. For example, in the case of an addition operation, theadder should start its operation as soon as it receives the addend andaugend words from the registers storing these words. Similarly, the sumword should be transferred from the adder as soon as the addition iscompleted, The time required to perform these operations varies from oneoperation to another and does so in a manner which is generally notpredictable. Further, in a particular data processing system underconsideration, the respective machine instruction signals (sometimesknown as operations signals) directing the operation of each stage tostart, have durations sufficient to permit very fast operation only ofeach stage. For example, in the case of addition, the duration of themachine instruction signal may be suiiicient to permit the addition ofaddend and augend words made up largely of zeros, but insufiicient topermit the worst case time, that is the time required to add two wordsmade up of all onesf In the latter case, the machine instruction signaldirecting the transfer lof the sum word out of the adder arrives wellbefore the addition is completed, and the machine instruction signaldirecting the addition of the two words terminates well prior to thetime that the addition has been completed.

A specific object of the present invention is to provide a circuit in anasynchronous data processing system which, in response to machine-instruction signals directing certain operations to be performed insequence, causes these operations to be performed in sequence and atappropriate times.

A more general object of the present invention is to provide a novelcircuit for producing an output in response to two signals which occur4in a given sequence, but only upon receipt of a third signal which mayoccur before or after the second occuring of the two signals.

Another object of the invention is to provide, in an asynchronous dataprocessing system, a circuit which, in response to the receipt of amachine instruction signal directing a certain operation to beperformed, causes the operation to be performed immediately if theprevious operation has been completed but which temporarily stores themachine instruction signal if the previous operation has not yet beencompleted, until the previous operation is completed.

One embodiment of the system of the invent-ion includes at least firstand second logic gates such as nor gates. The logical sum of the outputsof these gates is applied back through an inverter as a hold signal tothe first of these gates. So interconnected, a given change in thecondition of an input signal to the second gate, prior to the time thatthe input signal to the first gate has changed, produces no change inthe circuit output. How ever, the given change in the input signal tothe second gate after the input signal to the first gate has changedcauses the circuit to produce an output.

The invent-ion is described in -greater detail below and 'is'illustratedin the `following drawing of which:

Patented Mar. 22, 1966 rice FIGURES la-ld are diagrams to explain thesymbols employed in some of the remaining figures;

FIGURE 2 is a block circuit diagram of a portion of an asynchronousdigital data processing machine. This diagram is useful in explaining,by way of example, where in the machine the circuits of the presentinvention may be employed;

FIGURE 3 vis a drawing of a waveform present in various places in thecircuits of FIGURES 2, 4, 5 and 6;

FIGURE 4 is a block diagram of a circuit for generating an output signalwhen 'the transfer of a Word into a register has been completed;

FIGURE 5 is a block circuit diagram of one form of the presentinvention;

FIGUURE 6 is a block circuit diagram of another form of the presentinvention; and

FIGURE 7 is a block circuit diagram of a circuit which operatessimilarly to the circuit of FIG. 5.

Similar reference letters and numerals are used to represent similarelements in the various figures.

A number of blocks -shown in the various figures represent knowncircuits. The circuits of the blocks are actuated by electrical signalsappled to the blocks. When a signal is at one level, it represents thebinary digit 1 and when it is at another level it represents the binarydigit 0. For the sake of the discussion which follows, it may be assumed-that a positive-going signal represents the binary digit 1 and anegativeegoing signal represents the binary digit 0. Also, to simplifythe discussion, rather than speaking of an electrical signal beingapplied to a block or logic stage, it is sometimes stated that a 1 or a0 is applied to a block or level stage.

The symbols employed in the various figures are shown in FIGURE l.FIGURE la represents a binary storage circuit called a flip-flop. Asindicated by the truth table, when the flip-flop is set its l or Xoutput is 1, and its 0 or output is 0. When the flip-flop is reset, itsX output is 0 and its output is"1. FIGURE 1b shows a nor gate and itsBoolean equation as shown to the right of the gate. FIGURES 1c and 1dshow an and gate and an inverter, respectively.

The circuit shown in FIGURE 2 illustrates, by way of example, where inan asynchronous digital data processing machine the circuits of thepresent invention may be employed. It includes an n+1 wire bus whichcarries the bits of a binary word. The bus may come from the memorysystem (not shown) of the data processing machine. In a typical machinen+1 may equal 28 or 56 or some other large number of wires; however,only three of these wires are shown. The wires of the bus are connectedthrough and gates 10, 11 12 to the set terminals of ip-tlops 13, 14 15.(Again, only three of the n+1 gates and three of the n+1 f'lipops areshown.) These n+1 flip-flops make up the left register 16. As theflip-flop 13 stores the bit of least significance, it is legended 20flip-flop. In like manner since the last flip-flop 15 stores the bit ofmost significance, it is legended 211 flip-fiop. The wires of the busare also legended 20, 21 2n, corresponding to the significance of thebits the respective wires carry.

The respective wires of bus X are also connected through and gates V17,18 19 'to the set terminals of flip-Hops 20, 21 22. The latterflip-flops make up the right register 23.

and assigned to the same assignee as the present invention.

The sum output of the asynchronous binary adder is applied through andgates 26, 27 28 to the respective wires of the bus Y. This bus may leadback to a register (not shown) for temporarily storing the sum word.

The operation of the system shown in FIGURE 2 is Controlled by machine'instruction signals generated in the control unit (not shown) of thedata processing system. These machine instruction signals are shown atM11, M12 and M13 in FIGURE 3. As may be observed in FIG- URE 3, themachine instruction signals are relatively short and occur in timesequence. For example, the leading edge of machine instruction signalM12 may occur at about the same time as the lagging edge of the machineinstruction signal M11.

In the example chosen for illustration, it is assumed that the rightregister 23 of FIGURE 2 is storing a word. The machine instructionsignal M11 directs the transfer of a word from the bus X to the leftregister 16. Machine instruction signal M12 directs the asynchronousbinary adder to start adding the words in the two registors 16, 23. Themachine instruction signal M13 directs the binary adder to transfer thesum word to the output bus Y and thence to a register (not shown) Thevarious times required to perform the operations above vary fromoperation to operation.l As may be seen in FIGURE 3, for example, thetime At1 required to transfer a Word from a bus into the register isvariable and may be, although it is not necessarily, longer than theduration of the machine instruction signal M11. In a similar manner, thetime M2 required to perform the addition is also variable. Further, thetime A152 may start well after the time of machine instruction signalM12 has terminated and may end well after the time the machineinstruction signal M13 has arrived. Similarly, the Ytime Ata required toread-out the sum Word and apply it via the output Y bus to the register(not shown) which stores the sum word is also variable.

The circuit to be described converts the M11 signal to a read-in commandJ for the left register, as shown in FIGURE 3. This command has "aduration At1. It is applied to input terminal 29 of FIGURE 2 and servesas a priming signal for the and gates 10, 11 12 to the left register.The circuits to be described also convert the machine instruction signalM12 to the add command F (FIGURE 3) which is applied to the inputterminal 30 of FIGURE 2. The circuits to be described also convert themachine instruction signal M13 to the read-out sum command N which isapplied to the input terminal 31 of FIGURE 2. As can be seen from FIGURE3, these signals are appropriately timed and of proper duration.

The circuit shown in FIGURE includes ip-ops 80 and S2. The 1 output offlip-op 80 is the read-in command 1. The 0 output of ip-op 80 serves asan input to nor gate 84. The 1 output of ip-flop 82. serves as an inputto nor gate 86. Nor gate 86 is a one input gate and vis the logicalequivalent of an inverter. The logical sum C-i-D (the common connectionbetween leads 93 and 192 is the logical equivalent of an or gate) of theoutputs of nor gates 84 and 86 is applied via leads V93 and 92,respectively, to inverter 88. The output of the inverter 8 8 serves as asecond inf put to nor gate 84. It serves also as the add command F.

In the operation of 'thecircuit of FIGURE 5, flip-Hops and 82 areinitially both reset. Under these conditions 1, the read-in command, is0. Thus, the input andfpgates 10, 11 12 to the left register 16 ofFIGURE 2 are disabled. Similarly, F, the add com= mand, is 0. Thisdisables the asynchronous binary adder.

Assume noW that a 'Word is present on bus X and M11 occurs. M11 setsHip-flop 80, changes 1 to l. This primes the input and gates 10, 11 t 12(FIGURE 2) of the left register, and the data word ows through these andgates into the left register. The 0 output terminal of flip-Hop 80changes to 0; therefore A:0. B remains 0; therefore D:1, E:0, C:1; F,the add command, therefore remains 0.

1n the data processing machine under consideration, when the transfer ofa word has been completed, a signal G:1 occurs. This signal is appliedto the reset terminal of ip-ilop S0. The circuit for producing thesignal G is shown in FIGURE 4 and will be discussed shortly. However,for the purposes of the present discussion, it is assumed that thesecond machine instruction signal M12 occurs prior to the time that G:1occurs. Under these conditions, ip-flop 82 becomes set while ip-flop 80is also in its set condition. Since flip-Hop 80 remains set, J remains 1and the read-in command continues. However, B changes to 1. This changesD to 0, but as C remains 1, E remains 0. Since E is 0 and A is 0, Cremains 1; therefore F remains 0.

Summarizing the above, the premature arrival of machine instructionsignal MI2 does not terminate the readin Icorn-mand. Further, it doesnot cause the add command F to start. Y

Assume now that after the machine instruction signal M12 has arrived,.the transfer of the word from the bus X into the left register `hasbeen completed. This causes the generation of the signal G which resetsregister 80. This changes I to O, terminating the read-in command. Aalso changes to 1, causing C to change to 0. Flip-Hop 82 remains set sothat B is 1 and D is 0; therefore the logical sum C |D is 0, changing Eto 1 and changing the -add command F to l.

Summarizing the above, when the read-in is completed and the signal Goccurs after the M12 arrives, the read-in command J changes t0 0,terminating the read-in. Also, the add command F changes from 0 to 1,-causin-g the addition to start.

In some cases, the machine instruction signal M12 does not occur untilafter M11 and G have occurred. In this case, AB changes from 10 to 00,to 10 to 11 corresponding to the following four states of I and F: 1:0,F :0, 1:1, F:0; 1:0, F:0; 1:0, F:1. Under this set of conditions, theadd command starts concurrently with M12, a-s desired.

A number of the operations described above are given succinctly in thetable below:

Table l M11 G M12 E A B C D E F I 1 0 0 1 0 0 Start: both FFs reset.

1 0 0 1 1 0 1 Read-in command. 1 0 1 1 0 0 1 1 1 1 0 0 1 0 Add eommand=L1 1 0 0 1 0 0 Read-in eommand=0.

Read-out command=0.

The nor gate 94 shown at the left of FIGURE 5 is for the purpose ofindicating an error. Suppose MI1 should occur before the add command hasterminated. During the add command, F=1, B=1, A=l, D=0, Ezl, C=0. If nowM11 occurs, A changes to 0, and J, the read-in command, changes to 1.But D is 0, and E, which is 1, keeps C=; therefore F, the add command,remains 1. This is an undesired condition and is indicated by the outputT=1 which results because both A and C :0.

The circuit of FIGURE 5 is illustrated as there are a number of placesin asynchronous data processing machines where .the sequence ofoperations depend only upon two succes-sive machine instruction signals.To obtain commands from three successive machine instruction signals, anadditional circuit similar to a portion of the circuit of FIGURE 5 maytbe added to the circuit of FIGURE 5. The combined -circuit includingthe various feedback paths is shown in FIGURE 6. In addition to theelements of FIGURE 5, FIGURE 6 includes a third ip-flop 100. The norygate 86a connected to the 1 output of the flip-flop 100 is analogous tonor gate 86. The nor77 gate 84a and inverter 88a are analogous to norgate 84 and inverter 88, respectively. The feedback path carrying thesignal M .is analogous to the feedback path carrying the signal E.Interconnection 92a is analogous to the interconnection 92.

The operation of the circuit of FIGURE 6 is given succinctly in Table IIbelow:

Table FIGURE 4 shows the circuit for generating the readin completedsignal G shown as the third Waveform of FIGURE 3. It includes -a totalof n+1 logic stages, one stage for each wire of bus X, two of which, the.20 and 2n stages, are shown in FIGURE 4. Each `stage includes an andgate 102, a nor gate 104 and a nor gate 106. The nor gate 106 receivesthe outputs of and gates 102 and 104.

The bus X shown in FIGURE 4 is the bus X of FIG- URE 2. The bus Z inFIGURE 4 is the output bus connected to the 1 terminals of the leftregister 16 of FIGURE 2.

In the operation of the circuit of FIGURE 4, the transfer of a Word maybe considered to be completed when the word present at the l outputterminals of the ilipflops is equal to the Word present on the input busto the Hip-flop. In other words, the transfer is completed when the Wordon bus X equals the word on bus Z. Under these conditions, thecorresponding bits on each In the circuit of FIGURE 6, the errorcircuits analogous to nor gate 94 of FIGURE 5 are not shown. However,they may be present and may be interconnected similarly to nor circuit94.

In the circuit of FIGURE 5, .that part within block 200 includes norgate 84 or nor gate 86 (or its logical equivalent, an inverter), andinverter 88. It should be appreciated that alternate forms of thiscircuit are possible. One example is .the circuit of FIGURE 7 whichincludes and gate 202, inverter 204 and flip-Hop 206. And gate 202receives the signals A and B and applies its output to the set terminal(S) of flip-op 206. Inverter 204 receives signal B and applies itsoutput to the reset terminal (R) of flip-flop 206.

The operation of the circuit of FIGURE 7 is given in Table III below. Inthe table, E is the present state of the ip-flop, that is, `the value ofthe binary bit appearing at 1 output terminal. is the next value of Ewhich occurs in response to .the combination of bits AB applied to thecircuit 200. For exam-ple, the table shows that if E is presently 0, andA=1, B=1 are applied to circuit 200, E changes to 1, that is =1.Similarly, if E is presently 1 and A21, B=O are applied to circuit 200,E changes to 0. But, if E is presently 1 and A=0, B=1, then E remains 1.

bus are the same. For example, if the bit on the 20 wire is 1 on bus X,it is also 1 on bus Z. If so, and gate 102 is enabled, producing a loutput on lead 107 and this 1 output disables nor gate 106. Thisproduces a 0 on output lead 109. If, on the other hand, the 2 bit onboth buses is a 0, nor gate 104 becomes enabled and the bit on bus 109again becomes 0. It' the transfer is not completed, the correspondingbits, for example the 2 bit, may be unequal in which case gates 102 and104 will each produce a 0 output and nor gate 106 will produce a 1output.

The pulse generator 110 receives the logical sum of the outputs of the20 through the 2n stages. If the logical sum is 1, indicating that atleast one bit on bus X and its corresponding bit on bus Z are unequal,the pulse generator produces no output. However, when all bits areunequal, the logical sum of the 20 through 2n stages is 0. The pulsegenerator in response to this 0 input produces a 1 output signal G. Thisis the signal which is applied to the reset terminal of FIGURE 6.

Although not shown in FIGURE 2, a circuit similar to that of FIGURE 4may be employed to generate the signal I applied to the reset terminalof flip-flop 100. The buses between which the stages of FIG. 4 areconnected to generate this signal are the bus Y in FIGURE 2 and anotherbus (not shown) at the output of the register (not shown) which receivesthe sum word.

The circuits` for generating the read-in command for the right register23 may be similar to those for generating the read-in command for theleft register 16. These circuits for generating read-in commands respondto a fourth machine instruction signal (not shown). Separate circuitsfor generating the reset 1 and reset 2 signals of the left and rightregisters of FIGURE 2 are not shown. However, the reset 1 signal may bederived from the leading edge of the add command signal I. The circuitmay include a monostable multivibrator or similar pulse generatingcircuit. The reset 2 signal may be generated by a similar circuit.

While illustrated in terms of the control of an arithmetic operation, itshould be mentioned that the circuit of the present invention has manyother uses as a digital data processing machine. For example, there areplaces in the machine where it is sometimes desired to interrupt asequence of operations being performed but to do so only after the oneoperation being performed has been completed. In this case, the machineinstruction MI1 (FIG. 5) can be consided the start data processingsignal. This causes J to equal 1 and the data processing to begin. Ifnow, before the operation is completed, it is desired to stop thesequence of operations, a stop signal M12 can -be applied. However, thisstop signal will not be effective until the operation completed signal Goccurs. At that time, I becomes equal to 0 and F becomes equal to 1,where F, in this case, is a stop operation command.

In certain other places in the data processing machine, it may bedesired, unconditionally to stop an operation, regardless of Whether ornot it has been completed and to thereafter start the next operation.This can be accomplished by having a third input to nor gate 34 of FIG.5, which third input is normally a zero. M11 is now considered the startoperation signal and it may be assumed that it has occurred. Assume thatM12 has also occurred. M12 calls for the next operation to be started.On the other hand, the G equals 1 signal has not yet occurred. If nowthe third input to nor gate 84 is changed to a l, this unconditionallystops the operation called for by MI1 (even though not yet completed)and starts the operation called for by MI2.

In the discussion of FIG. 5, it is mentioned that a one input nor gatesuch as 86 is the logical equivalent of an inverter. In a number of theclaims, this gate is referred to as an inverter.

What is claimed is:

1. In combination, a nor gate; an inverter; means for producing thecomplement of the logical sum of the inverter and nor7 gate outputs; anda feedback circuit means for applying saidl complement to the nor gate.

2. In the combination set forth in claim 1, said inverter comprising aone input nor gate.

3. In combination, a two input nor gate; an inverter; means forproducing the complement of the logical sum of the inverter and nor gateoutputs; a feedback circuit means for applying said complement to oneinput of the nor gate; and means for applying signals indicative ofbinary digits to the second input to the nor gate and inverter,respectively.

4, In combination?, a nor gate having two input ter.-

minals, one for receiving an input signal; a first inverter having aninput terminal for receiving an input signal; a second inverter; meansfor deriving a signal indicative of the logical sum of the outputsignals of the nor gate and first inverter and applying said signal tosaid second inverter; and means for applying the output signal of saidsecond inverter to the second input terminal of the nor gate.

5. In combination,

a nor gate having two input terminals, the rst for receiving a iirstinput signal indicative of a binary digit;

a first inverter having an input terminal for receiving a second inputsignal indicative of a binary digit;

a second inverter;

means for producing a signal indicative of the logical sum of the outputsignals of the nor gate and first inverter and applying that signalthrough the second inverter to the second input terminal of the norgate; v

and means coupled to the first input terminal of the nor gate and theoutput circuit of the nor gate for indicating the presence of a zero atboth points concurrently.

6. In combination,

a iirst nor gate having two input terminals, one for receiving a iirstinput signal;

-a irst inverter having an input terminal for receiving a second inputsignal;

a second inverter;

means for producing a signal indicative of the logical sum of the outputsignals of the rst nor gate and rst inverter and applying that signalthrough the second inverter to the second input terminal of the firstnor gate;

a second nor gate having two input terminals, the rst connected toreceive the signal indicative of the logical sum of the output signalsof the rst nor gate and first inverter;

a third inverter having an input terminal for receiving a third inputsignal;

a fourth inverter;

and means for producing a signal indicative of the logical sum of theoutput signals of the second nor gate and third inverter and applyingthat signal through the fourth inverter to the second input terminal tothe second nor gate.

References Cited by the Examiner UNITED STATES PATENTS 2,998,191 8/1961Marshall 23S-153 3,058,656 10/1962 Pomerene 23S-153 3,067,934 12/1962Amacher et al.

3,075,089 l/1963 Maley.

3,083,305 3/1963 Maley.

3,103,577 10/1963 Willard 328-93 X 3,107,306 10/1963 Dobbie 307-88.53,113,273 12/1963 Tendick 307-885 3,162,816 12/1964 Rakoczi et al307-885 ARTHUR GAUSS, Primary Examiner.

MALCOLM A. MORRISON, Examiner.

M, POKOTILOW, I. C. EDELL,V AssslantvExaminers.

1. IN COMBINATION, A "NOR" GATE; AN INVERTER; MEANS FOR PRODUCING THECOMPLEMENT OF THE LOGICAL SUM OF THE INVERTER AND "NOR" GATE OUTPUTS;AND A FEEDBACK CIRCUIT MEANS FOR APPLYING SAID COMPLEMENT TO THE "NOR"GATE.